dali/bacnet_stack
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Updated fuses for BDK.

Browse Source
This commit is contained in:
skarg
2009-08-12 17:43:12 +00:00
parent b8efa8deb5
commit 62e58fce27
2 changed files with 58 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bacnet-stack/ports/bdk-atxx4-mstp/Makefile
-1
View File
@@ -147,7 +147,6 @@ OPTIMIZATION = -Os $(OPTIMIZE_FLAGS)
DEBUGGING = DEBUGGING =
endif endif
## BACnet options ## BACnet options
BFLAGS = -DBACDL_MSTP BFLAGS = -DBACDL_MSTP
BFLAGS += -DMAX_APDU=128 BFLAGS += -DMAX_APDU=128
bacnet-stack/ports/bdk-atxx4-mstp/fuses.c
+58 -26
View File
@@ -27,36 +27,68 @@
#if defined(__GNUC__) && (__GNUC__ > 4) #if defined(__GNUC__) && (__GNUC__ > 4)
/* AVR fuse settings for ATmega644P */ /* AVR fuse settings for ATmega644P */
FUSES = { FUSES = {
/* == LOW FUSE or LFUSE settings == */
/* CKSEL3..0- Clock Select Configuration
CKSEL3 CKSEL2 CKSEL1 CKSEL0 Description
1 1 1 x 1111-1000=Low Power Crystal Oscillator
0 1 1 x 0111-0110=Full Swing Crystal Oscillator
0 1 0 x 0101-0100=Low Frequency Crystal Oscillator
0 0 1 1 Internal 128kHz RC Oscillator
0 0 1 0 Calibrated Internal RC Oscillator
0 0 0 0 External Clock]
SUT1..0 - Clock Start Up Time selection
If CKSEL0=0, then SUT1..0 is 14CK+: 00=4.1ms,01=65ms,10=BOD,11=4.1ms
If CKSEL0=1, then SUT1..0 is 14CK+: 00=65ms,01=BOD,10=4.1ms,11=65ms
BOD means wait until internal Brown Out Detect Voltage is sufficient.
*/
/* CKOUT: clock output on CKOUT pin */
/* CKDIV8: divide clock by 8 */
/* External Ceramic Resonator - configuration */ /* External Ceramic Resonator - configuration */
/* Full Swing Crystal Oscillator Clock Selection */ /* Full Swing Crystal Oscillator Clock Selection */
/* Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms */ /* Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms */
/* .low = (FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1), */
/* Crystal Oscillator, 16K CK + 14CK + BOD Enabled */
/* note: fuses are enabled by clearing the bit, so /* note: fuses are enabled by clearing the bit, so
any fuses listed below are cleared fuses. */ any fuses listed below are cleared fuses,
.low = (FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1), or are CKSEL or SUT bits that are zero. */
/* BOOTSZ configuration: .low = (FUSE_CKSEL3 & FUSE_SUT1),
BOOTSZ1 BOOTSZ0 Boot Size
------- ------- --------- /* == HIGH FUSE or HFUSE settings == */
1 1 512 /* BOOTRST: Enable Bootloader Reset Vector */
1 0 1024 /* EESAVE: Enable preserve EEPROM on Chip Erase */
0 1 2048 /* WDTON: Enable watchdog timer always on */
0 0 4096 /* SPIEN: Enable Serial Program and Data Downloading */
*/ /* JTAGEN: Enable JTAG */
/* note: fuses are enabled by clearing the bit, so /* OCDEN: Enable OCD */
any fuses listed below are cleared fuses. */ /* BOOTSZ configuration:
.high = BOOTSZ1 BOOTSZ0 Boot Size
(FUSE_BOOTSZ1 & FUSE_BOOTRST & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), ------- ------- ---------
/* Brown-out detection VCC=2.7V */ 1 1 512
/* BODLEVEL configuration 1 0 1024
BODLEVEL2 BODLEVEL1 BODLEVEL0 Voltage 0 1 2048
--------- --------- --------- -------- 0 0 4096
1 1 1 disabled */
1 1 0 1.8V /* note: fuses are enabled by clearing the bit, so
1 0 1 2.7V any fuses listed below are cleared fuses,
1 0 0 4.3V or are BOOTSZ bits that are zero. */
*/ .high =
/* note: fuses are enabled by clearing the bit, so (FUSE_BOOTSZ1 & FUSE_BOOTRST & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
any fuses listed below are cleared fuses. */
.extended = (FUSE_BODLEVEL1 & FUSE_BODLEVEL0) /* == EXTENDED FUSE or EFUSE settings == */
/* BODLEVEL configuration
BODLEVEL2 BODLEVEL1 BODLEVEL0 Voltage
--------- --------- --------- --------
1 1 1 disabled
1 1 0 1.8V
1 0 1 2.7V
1 0 0 4.3V
*/
/* note: fuses are enabled by clearing the bit, so
any fuses listed below are cleared fuses,
or are BODLEVEL bits that are zero. */
/* Brown-out detection VCC=2.7V */
.extended = (FUSE_BODLEVEL1 & FUSE_BODLEVEL0)
}; };
/* AVR lock bits - unlocked */ /* AVR lock bits - unlocked */