dali/bacnet_stack
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This commit is contained in:
skarg
2007-11-29 15:56:53 +00:00
parent c585241c03
commit 411d6c1b24
236 changed files with 17864 additions and 15724 deletions
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bacnet-stack/ports/at91sam7s/init.c
+24 -23
View File
@@ -20,9 +20,12 @@
// The following functions must be write in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
extern void AT91F_Spurious_handler(
void);
extern void AT91F_Default_IRQ_handler(
void);
extern void AT91F_Default_FIQ_handler(
void);
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
@@ -30,31 +33,33 @@ extern void AT91F_Default_FIQ_handler(void);
//* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void LowLevelInit(void)
void LowLevelInit(
void)
{
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set Flash Wait sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 48054841 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
// result: AT91C_MC_FMR = 0x00320100 (MC Flash Mode Register)
AT91C_BASE_MC->MC_FMR = (((AT91C_MC_FMCN) & (50 <<16)) | AT91C_MC_FWS_1FWS);
AT91C_BASE_MC->MC_FMR =
(((AT91C_MC_FMCN) & (50 << 16)) | AT91C_MC_FWS_1FWS);
//* Watchdog Disable
// result: AT91C_WDTC_WDMR = 0x00008000 (Watchdog Mode Register)
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
//* Set MCK at 48 054 841
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSecond
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
// result: AT91C_CKGR_MOR = 0x00000601 (Main Oscillator Register)
pPMC->PMC_MOR = ((AT91C_CKGR_OSCOUNT & (0x06<<8)) | AT91C_CKGR_MOSCEN);
pPMC->PMC_MOR = ((AT91C_CKGR_OSCOUNT & (0x06 << 8)) | AT91C_CKGR_MOSCEN);
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
while (!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// PMC Clock Generator PLL Register setup
//
// The following settings are used: DIV = 14
@@ -73,12 +78,11 @@ void LowLevelInit(void)
// OUT = 0 (not used)
// result: AT91C_CKGR_PLLR = 0x00000000480A0E (PLL Register)
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14) |
(AT91C_CKGR_PLLCOUNT & (10<<8)) |
(AT91C_CKGR_MUL & (72<<16)));
(AT91C_CKGR_PLLCOUNT & (10 << 8)) | (AT91C_CKGR_MUL & (72 << 16)));
// Wait the startup time (until PMC Status register LOCK bit is set)
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
while (!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// PMC Master Clock (MCK) Register setup
//
// CSS = 3 (PLLCK clock selected)
@@ -88,14 +92,11 @@ void LowLevelInit(void)
// Note: Master Clock MCK = 48054841 hz (this is the CPU clock speed)
// result: AT91C_PMC_MCKR = 0x00000007 (Master Clock Register)
pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2;
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
for (i = 1; i < 31; i++)
{
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
}
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler;
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler;
}