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Strip tabs and trailing white spaces, and fix end of files (#748)

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* format: Strip trailing whitespaces

We want to get rid of trailing whitespaces completly as they make just git
noice. Much better to start using automated tools to get rid of them once and
not getting them back again. This way git history will be cleaner and review
easier.

Commit was generated with:

    pre-commit run --all-files trailing-whitespace

* format: Files should have exactly one new line end of them

It is good practice that every file has one new line. It is not now days so
mandatory but it also is not nice if file has lot of newlines end of it. We will
use pre-commit which takes automatically care about this so let's fix all.

Commit was generated with:

    pre-commit run --all-files end-of-file-fixer

* format: Convert tabs to spaces

Project mostly use spaces over tabs. When mixing tabs and spaces this usually
makes formatting issues and also when changing those in commits it will make lot
of git noise. We will force spaces most of the time and use pre-commit to fix.

Commit was generated with:

    pre-commit run --all-files remove-tabs

---------

Co-authored-by: Kari Argillander <kari.argillander@fidelix.com>
This commit is contained in:
Kari Argillander
2024-08-25 22:13:57 +03:00
committed by GitHub
parent 9e0657424e
commit 369da70f2a
455 changed files with 7147 additions and 7249 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ports/arduino_uno/bip.c
+1 -1
View File
@@ -202,7 +202,7 @@ int bip_send_pdu(BACNET_ADDRESS *dest, /* destination address */
*
* @param src [out] Source of the packet - who should receive any response.
* @param pdu [out] A buffer to hold the PDU portion of the received packet,
* after the BVLC portion has been stripped
* after the BVLC portion has been stripped
* off.
* @param max_pdu [in] Size of the pdu[] buffer.
* @param timeout [in] The number of milliseconds to wait for a packet.
ports/at91sam7s/.gdbinit
-1
View File
@@ -13,4 +13,3 @@ monitor long 0xfffffc30 0x7
monitor sleep 100
monitor long 0xfffffd08 0xa5000401
monitor sleep 100
ports/at91sam7s/CMakeLists.txt
+5 -5
View File
@@ -200,13 +200,13 @@ target_compile_definitions(${EXECUTABLE} PRIVATE
target_compile_options(${EXECUTABLE} PRIVATE
-Wall -Wextra -pedantic
-Wfloat-equal -Wconversion -Wredundant-decls
-Wfloat-equal -Wconversion -Wredundant-decls
-Wswitch-default
# don't warn about conversion, sign, compares, long long and attributes
# since they are common in embedded
-Wno-sign-conversion
-Wno-sign-conversion
-Wno-conversion
-Wno-sign-compare
-Wno-sign-compare
-Wno-long-long
-Wno-attributes
# don't warn about implicit fallthrough since it is common in network protocols
@@ -259,7 +259,7 @@ add_custom_target(symbols
)
# calculate the worst case CSTACK memory usage by size and place into a file
add_custom_target(cstack
add_custom_target(cstack
DEPENDS ${EXECUTABLE}
COMMENT "Print CSTACK memory depth by size"
COMMAND ${CMAKE_CSTACK} ${EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR} 1> ${PROJECT_NAME}.su
@@ -269,7 +269,7 @@ add_custom_target(cstack
)
# Print file and library sizes
add_custom_target(memmap
add_custom_target(memmap
DEPENDS ${PROJECT_NAME}.map
COMMENT "Print file and library memory usage by size"
COMMAND ${CMAKE_MEMAP} -t GCC_ARM ${PROJECT_NAME}.map
ports/at91sam7s/at91sam7s256.h
+571 -571
View File
File diff suppressed because it is too large Load Diff
ports/at91sam7s/at91sam7s256.ld
+35 -36
View File
@@ -2,8 +2,8 @@
/* LINKER SCRIPT */
/* */
/* */
/* The Linker Script defines how the code and data emitted by the GNU C compiler and assembler are */
/* to be loaded into memory (code goes into FLASH, variables go into RAM). */
/* The Linker Script defines how the code and data emitted by the GNU C compiler and assembler are */
/* to be loaded into memory (code goes into FLASH, variables go into RAM). */
/* */
/* Any symbols defined in the Linker Script are automatically global and available to the rest of the */
/* program. */
@@ -11,7 +11,7 @@
/* To force the linker to use this LINKER SCRIPT, just add the -T AT91SAM7S256.LD */
/* directive to the linker flags in the makefile. For example, */
/* */
/* LFLAGS = -Map main.map -nostartfiles -T AT91SAM7S256.LD */
/* LFLAGS = -Map main.map -nostartfiles -T AT91SAM7S256.LD */
/* */
/* */
/* The order that the object files are listed in the makefile determines what .text section is */
@@ -19,10 +19,10 @@
/* */
/* For example: $(LD) $(LFLAGS) -o main.out crt.o main.o lowlevelinit.o */
/* */
/* crt.o is first in the list of objects, so it will be placed at address 0x00000000 */
/* crt.o is first in the list of objects, so it will be placed at address 0x00000000 */
/* */
/* */
/* The top of the stack (_stack_end) is (last_byte_of_ram +1) - 4 */
/* The top of the stack (_stack_end) is (last_byte_of_ram +1) - 4 */
/* */
/* Therefore: _stack_end = (0x00020FFFF + 1) - 4 = 0x00210000 - 4 = 0x0020FFFC */
/* Therefore: _stack_end = (0x000203FFF + 1) - 4 = 0x00204000 - 4 = 0x00203FFC */
@@ -57,7 +57,7 @@
/* . | SVC Stack 16 bytes | */
/* . | | */
/* . |---------------------------------|0x0020FECC */
/* . | | */
/* . | | */
/* . | stack area for user program | */
/* . | | */
/* . | | */
@@ -110,10 +110,10 @@
ENTRY(_vec_reset)
/* specify the AT91SAM7S64 memory areas */
MEMORY
MEMORY
{
flash : ORIGIN = 0, LENGTH = 64K /* FLASH EPROM */
ram : ORIGIN = 0x00200000, LENGTH = 16K /* static RAM area */
flash : ORIGIN = 0, LENGTH = 64K /* FLASH EPROM */
ram : ORIGIN = 0x00200000, LENGTH = 16K /* static RAM area */
}
@@ -122,35 +122,34 @@ MEMORY
_stack_end = 0x203FFC;
/* now define the output sections */
SECTIONS
SECTIONS
{
. = 0; /* set location counter to address zero */
.text : /* collect all sections that should go into FLASH after startup */
{
*(.text*) /* all .text sections (code) */
*(.rodata) /* all .rodata sections (constants, strings, etc.) */
*(.rodata*) /* all .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* all .glue_7 sections (no idea what these are) */
*(.glue_7t) /* all .glue_7t sections (no idea what these are) */
_etext = .; /* define a global symbol _etext just after the last code byte */
} >flash /* put all the above into FLASH */
. = 0; /* set location counter to address zero */
.data : /* collect all initialized .data sections that go into RAM */
{
_data = .; /* create a global symbol marking the start of the .data section */
*(.data*) /* all .data sections */
_edata = .; /* define a global symbol marking the end of the .data section */
} >ram AT >flash /* put all the above into RAM (but load the LMA initializer copy into FLASH) */
.text : /* collect all sections that should go into FLASH after startup */
{
*(.text*) /* all .text sections (code) */
*(.rodata) /* all .rodata sections (constants, strings, etc.) */
*(.rodata*) /* all .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* all .glue_7 sections (no idea what these are) */
*(.glue_7t) /* all .glue_7t sections (no idea what these are) */
_etext = .; /* define a global symbol _etext just after the last code byte */
} >flash /* put all the above into FLASH */
.bss : /* collect all uninitialized .bss sections that go into RAM */
{
_bss_start = .; /* define a global symbol marking the start of the .bss section */
*(.bss*) /* all .bss sections */
} >ram /* put all the above in RAM (it will be cleared in the startup code */
.data : /* collect all initialized .data sections that go into RAM */
{
_data = .; /* create a global symbol marking the start of the .data section */
*(.data*) /* all .data sections */
_edata = .; /* define a global symbol marking the end of the .data section */
} >ram AT >flash /* put all the above into RAM (but load the LMA initializer copy into FLASH) */
. = ALIGN(4); /* advance location counter to the next 32-bit boundary */
_bss_end = . ; /* define a global symbol marking the end of the .bss section */
.bss : /* collect all uninitialized .bss sections that go into RAM */
{
_bss_start = .; /* define a global symbol marking the start of the .bss section */
*(.bss*) /* all .bss sections */
} >ram /* put all the above in RAM (it will be cleared in the startup code */
. = ALIGN(4); /* advance location counter to the next 32-bit boundary */
_bss_end = . ; /* define a global symbol marking the end of the .bss section */
}
_end = .; /* define a global symbol marking the end of application RAM */
_end = .; /* define a global symbol marking the end of application RAM */
ports/at91sam7s/bacnet.ewp
+2 -2
View File
@@ -78,7 +78,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>AT91SAM7S256 Atmel AT91SAM7S256</state>
<state>AT91SAM7S256 Atmel AT91SAM7S256</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@@ -138,7 +138,7 @@
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>AT91SAM7S256 Atmel AT91SAM7S256</state>
<state>AT91SAM7S256 Atmel AT91SAM7S256</state>
</option>
<option>
<name>FPU2</name>
ports/at91sam7s/bacnet.eww
-2
View File
@@ -6,5 +6,3 @@
</project>
<batchBuild/>
</workspace>
ports/at91sam7s/board.h
+31 -31
View File
@@ -24,57 +24,57 @@
/*----------------------------------------------- */
/* The AT91SAM7S2564 embeds a 64-Kbyte SRAM bank, and 256 K-Byte Flash */
#define INT_SRAM 0x00200000
#define INT_SRAM_REMAP 0x00000000
#define INT_SRAM 0x00200000
#define INT_SRAM_REMAP 0x00000000
#define INT_FLASH 0x00000000
#define INT_FLASH_REMAP 0x01000000
#define INT_FLASH 0x00000000
#define INT_FLASH_REMAP 0x01000000
#define FLASH_PAGE_NB 512
#define FLASH_PAGE_SIZE 128
#define FLASH_PAGE_NB 512
#define FLASH_PAGE_SIZE 128
/*------------------------ */
/* Leds Definition */
/*------------------------ */
#define LED1 (1<<0) /* PA0 */
#define LED2 (1<<1) /* PA1 */
#define LED3 (1<<2) /* PA2 */
#define LED4 (1<<3) /* PA3 */
#define NB_LEB 4
#define LED_MASK (LED1|LED2|LED3|LED4)
#define LED1 (1<<0) /* PA0 */
#define LED2 (1<<1) /* PA1 */
#define LED3 (1<<2) /* PA2 */
#define LED4 (1<<3) /* PA3 */
#define NB_LEB 4
#define LED_MASK (LED1|LED2|LED3|LED4)
/*---------------------------------- */
/* Push Buttons Definition */
/*----------------------------------- */
#define SW1_MASK (1<<19) /* PA19 */
#define SW2_MASK (1<<20) /* PA20 */
#define SW3_MASK (1<<15) /* PA15 */
#define SW4_MASK (1<<14) /* PA14 */
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1_MASK (1<<19) /* PA19 */
#define SW2_MASK (1<<20) /* PA20 */
#define SW3_MASK (1<<15) /* PA15 */
#define SW4_MASK (1<<14) /* PA14 */
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1 (1<<19) /* PA19 */
#define SW2 (1<<20) /* PA20 */
#define SW3 (1<<15) /* PA15 */
#define SW4 (1<<14) /* PA14 */
#define SW1 (1<<19) /* PA19 */
#define SW2 (1<<20) /* PA20 */
#define SW3 (1<<15) /* PA15 */
#define SW4 (1<<14) /* PA14 */
/*------------------------- */
/* USART Definition */
/*------------------------- */
/* SUB-D 9 points J3 DBGU */
#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD 115200 /* Baud rate */
#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD 115200 /* Baud rate */
#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
/*-------------- */
/* Master Clock */
/*-------------- */
#define EXT_OC 18432000 /* Exetrnal ocilator MAINCK */
#define MCK 47923200 /* MCK (PLLRC div by 2) */
#define MCKKHz (MCK/1000) /* */
#define EXT_OC 18432000 /* Exetrnal ocilator MAINCK */
#define MCK 47923200 /* MCK (PLLRC div by 2) */
#define MCKKHz (MCK/1000) /* */
#endif /* Board_h */
ports/at91sam7s/crt.s
+179 -179
View File
@@ -1,40 +1,40 @@
/* ****************************************************************************************************** */
/* crt.s */
/* crt.s */
/* */
/* Assembly Language Startup Code for Atmel AT91SAM7S256 */
/* */
/* */
/* */
/* */
/* */
/* */
/* Author: James P Lynch May 12, 2007 */
/* ****************************************************************************************************** */
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000010 /* stack for "undefined instruction" interrupts is 16 bytes */
.set ABT_STACK_SIZE, 0x00000010 /* stack for "abort" interrupts is 16 bytes */
.set FIQ_STACK_SIZE, 0x00000080 /* stack for "FIQ" interrupts is 128 bytes */
.set IRQ_STACK_SIZE, 0X00000080 /* stack for "IRQ" normal interrupts is 128 bytes */
.set SVC_STACK_SIZE, 0x00000080 /* stack for "SVC" supervisor mode is 128 bytes */
.set UND_STACK_SIZE, 0x00000010 /* stack for "undefined instruction" interrupts is 16 bytes */
.set ABT_STACK_SIZE, 0x00000010 /* stack for "abort" interrupts is 16 bytes */
.set FIQ_STACK_SIZE, 0x00000080 /* stack for "FIQ" interrupts is 128 bytes */
.set IRQ_STACK_SIZE, 0X00000080 /* stack for "IRQ" normal interrupts is 128 bytes */
.set SVC_STACK_SIZE, 0x00000080 /* stack for "SVC" supervisor mode is 128 bytes */
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */
.set ARM_MODE_USR, 0x10 /* Normal User Mode */
.set ARM_MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
.set ARM_MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
.set ARM_MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
.set ARM_MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
.set ARM_MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
.set ARM_MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */
.set ARM_MODE_USR, 0x10 /* Normal User Mode */
.set ARM_MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
.set ARM_MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
.set ARM_MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
.set ARM_MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
.set ARM_MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
.set ARM_MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
/* Addresses and offsets of AIC and PIO */
.set AT91C_BASE_AIC, 0xFFFFF000 /* (AIC) Base Address */
.set AT91C_PIOA_CODR, 0xFFFFF434 /* (PIO) Clear Output Data Register */
.set AT91C_AIC_IVR, 0xFFFFF100 /* (AIC) IRQ Interrupt Vector Register */
.set AT91C_AIC_FVR, 0xFFFFF104 /* (AIC) FIQ Interrupt Vector Register */
.set AIC_IVR, 256 /* IRQ Vector Register offset from base above */
.set AIC_FVR, 260 /* FIQ Vector Register offset from base above */
.set AIC_EOICR, 304 /* End of Interrupt Command Register */
.set AT91C_BASE_AIC, 0xFFFFF000 /* (AIC) Base Address */
.set AT91C_PIOA_CODR, 0xFFFFF434 /* (PIO) Clear Output Data Register */
.set AT91C_AIC_IVR, 0xFFFFF100 /* (AIC) IRQ Interrupt Vector Register */
.set AT91C_AIC_FVR, 0xFFFFF104 /* (AIC) FIQ Interrupt Vector Register */
.set AIC_IVR, 256 /* IRQ Vector Register offset from base above */
.set AIC_FVR, 260 /* FIQ Vector Register offset from base above */
.set AIC_EOICR, 304 /* End of Interrupt Command Register */
/* identify all GLOBAL symbols */
.global _vec_reset
@@ -46,165 +46,165 @@
.global _vec_irq
.global _vec_fiq
.global AT91F_Irq_Handler
.global AT91F_Fiq_Handler
.global AT91F_Default_FIQ_handler
.global AT91F_Default_IRQ_handler
.global AT91F_Spurious_handler
.global AT91F_Dabt_Handler
.global AT91F_Pabt_Handler
.global AT91F_Undef_Handler
.global AT91F_Fiq_Handler
.global AT91F_Default_FIQ_handler
.global AT91F_Default_IRQ_handler
.global AT91F_Spurious_handler
.global AT91F_Dabt_Handler
.global AT91F_Pabt_Handler
.global AT91F_Undef_Handler
/* GNU assembler controls */
.text /* all assembler code that follows will go into .text section */
.arm /* compile for 32-bit ARM instruction set */
.align /* align section on 32-bit boundary */
.text /* all assembler code that follows will go into .text section */
.arm /* compile for 32-bit ARM instruction set */
.align /* align section on 32-bit boundary */
/* ============================================================ */
/* VECTOR TABLE */
/* */
/* Must be located in FLASH at address 0x00000000 */
/* */
/* Easy to do if this file crt.s is first in the list */
/* for the linker step in the makefile, e.g. */
/* */
/* $(LD) $(LFLAGS) -o main.out crt.o main.o */
/* */
/* VECTOR TABLE */
/* */
/* Must be located in FLASH at address 0x00000000 */
/* */
/* Easy to do if this file crt.s is first in the list */
/* for the linker step in the makefile, e.g. */
/* */
/* $(LD) $(LFLAGS) -o main.out crt.o main.o */
/* */
/* ============================================================ */
_vec_reset: b _init_reset /* RESET vector - must be at 0x00000000 */
_vec_undef: b AT91F_Undef_Handler /* Undefined Instruction vector */
_vec_swi: b _vec_swi /* Software Interrupt vector */
_vec_pabt: b AT91F_Pabt_Handler /* Prefetch abort vector */
_vec_dabt: b AT91F_Dabt_Handler /* Data abort vector */
_vec_rsv: nop /* Reserved vector */
_vec_irq: b AT91F_Irq_Handler /* Interrupt Request (IRQ) vector */
_vec_fiq: /* Fast interrupt request (FIQ) vector */
_vec_reset: b _init_reset /* RESET vector - must be at 0x00000000 */
_vec_undef: b AT91F_Undef_Handler /* Undefined Instruction vector */
_vec_swi: b _vec_swi /* Software Interrupt vector */
_vec_pabt: b AT91F_Pabt_Handler /* Prefetch abort vector */
_vec_dabt: b AT91F_Dabt_Handler /* Data abort vector */
_vec_rsv: nop /* Reserved vector */
_vec_irq: b AT91F_Irq_Handler /* Interrupt Request (IRQ) vector */
_vec_fiq: /* Fast interrupt request (FIQ) vector */
/* ======================================================================== */
/* Function: AT91F_Fiq_Handler */
/* */
/* Function: AT91F_Fiq_Handler */
/* */
/* The FIQ interrupt asserts when switch SW1 is pressed. */
/* */
/* */
/* This simple FIQ handler turns on LED3 (Port PA2). The LED3 will be */
/* turned off by the background loop in main() thus giving a visual */
/* indication that the interrupt has occurred. */
/* */
/* This FIQ_Handler supports non-nested FIQ interrupts (a FIQ interrupt */
/* cannot itself be interrupted). */
/* */
/* */
/* This FIQ_Handler supports non-nested FIQ interrupts (a FIQ interrupt */
/* cannot itself be interrupted). */
/* */
/* The Fast Interrupt Vector Register (AIC_FVR) is read to clear the */
/* interrupt. */
/* */
/* A global variable FiqCount is also incremented. */
/* */
/* Remember that switch SW1 is not debounced, so the FIQ interrupt may */
/* interrupt. */
/* */
/* A global variable FiqCount is also incremented. */
/* */
/* Remember that switch SW1 is not debounced, so the FIQ interrupt may */
/* occur more than once for a single button push. */
/* */
/* Programmer: James P Lynch */
/* */
/* Programmer: James P Lynch */
/* ======================================================================== */
AT91F_Fiq_Handler:
/* Adjust LR_irq */
sub lr, lr, #4
sub lr, lr, #4
/* Read the AIC Fast Interrupt Vector register to clear the interrupt */
ldr r12, =AT91C_AIC_FVR
ldr r11, [r12]
ldr r12, =AT91C_AIC_FVR
ldr r11, [r12]
/* Return from Fiq interrupt */
movs pc, lr
movs pc, lr
/* ======================================================================== */
/* _init_reset Handler */
/* */
/* RESET vector 0x00000000 branches to here. */
/* */
/* ARM microprocessor begins execution after RESET at address 0x00000000 */
/* in Supervisor mode with interrupts disabled! */
/* */
/* _init_reset handler: creates a stack for each ARM mode. */
/* sets up a stack pointer for each ARM mode. */
/* turns off interrupts in each mode. */
/* leaves CPU in SYS (System) mode. */
/* */
/* block copies the initializers to .data section */
/* clears the .bss section to zero */
/* */
/* branches to main( ) */
/* _init_reset Handler */
/* */
/* RESET vector 0x00000000 branches to here. */
/* */
/* ARM microprocessor begins execution after RESET at address 0x00000000 */
/* in Supervisor mode with interrupts disabled! */
/* */
/* _init_reset handler: creates a stack for each ARM mode. */
/* sets up a stack pointer for each ARM mode. */
/* turns off interrupts in each mode. */
/* leaves CPU in SYS (System) mode. */
/* */
/* block copies the initializers to .data section */
/* clears the .bss section to zero */
/* */
/* branches to main( ) */
/* ======================================================================== */
.text /* all assembler code that follows will go into .text section */
.align /* align section on 32-bit boundary */
.text /* all assembler code that follows will go into .text section */
.align /* align section on 32-bit boundary */
_init_reset:
/* Setup a stack for each mode with interrupts initially disabled. */
ldr r0, =_stack_end /* r0 = top-of-stack */
/* Setup a stack for each mode with interrupts initially disabled. */
ldr r0, =_stack_end /* r0 = top-of-stack */
msr CPSR_c, #ARM_MODE_UND|I_BIT|F_BIT /* switch to Undefined Instruction Mode */
mov sp, r0 /* set stack pointer for UND mode */
sub r0, r0, #UND_STACK_SIZE /* adjust r0 past UND stack */
msr CPSR_c, #ARM_MODE_UND|I_BIT|F_BIT /* switch to Undefined Instruction Mode */
mov sp, r0 /* set stack pointer for UND mode */
sub r0, r0, #UND_STACK_SIZE /* adjust r0 past UND stack */
msr CPSR_c, #ARM_MODE_ABT|I_BIT|F_BIT /* switch to Abort Mode */
mov sp, r0 /* set stack pointer for ABT mode */
sub r0, r0, #ABT_STACK_SIZE /* adjust r0 past ABT stack */
msr CPSR_c, #ARM_MODE_ABT|I_BIT|F_BIT /* switch to Abort Mode */
mov sp, r0 /* set stack pointer for ABT mode */
sub r0, r0, #ABT_STACK_SIZE /* adjust r0 past ABT stack */
msr CPSR_c, #ARM_MODE_FIQ|I_BIT|F_BIT /* switch to FIQ Mode */
mov sp, r0 /* set stack pointer for FIQ mode */
sub r0, r0, #FIQ_STACK_SIZE /* adjust r0 past FIQ stack */
msr CPSR_c, #ARM_MODE_FIQ|I_BIT|F_BIT /* switch to FIQ Mode */
mov sp, r0 /* set stack pointer for FIQ mode */
sub r0, r0, #FIQ_STACK_SIZE /* adjust r0 past FIQ stack */
msr CPSR_c, #ARM_MODE_IRQ|I_BIT|F_BIT /* switch to IRQ Mode */
mov sp, r0 /* set stack pointer for IRQ mode */
sub r0, r0, #IRQ_STACK_SIZE /* adjust r0 past IRQ stack */
msr CPSR_c, #ARM_MODE_IRQ|I_BIT|F_BIT /* switch to IRQ Mode */
mov sp, r0 /* set stack pointer for IRQ mode */
sub r0, r0, #IRQ_STACK_SIZE /* adjust r0 past IRQ stack */
msr CPSR_c, #ARM_MODE_SVC|I_BIT|F_BIT /* switch to Supervisor Mode */
mov sp, r0 /* set stack pointer for SVC mode */
sub r0, r0, #SVC_STACK_SIZE /* adjust r0 past SVC stack */
msr CPSR_c, #ARM_MODE_SVC|I_BIT|F_BIT /* switch to Supervisor Mode */
mov sp, r0 /* set stack pointer for SVC mode */
sub r0, r0, #SVC_STACK_SIZE /* adjust r0 past SVC stack */
msr CPSR_c, #ARM_MODE_SYS|I_BIT|F_BIT /* switch to System Mode */
mov sp, r0 /* set stack pointer for SYS mode */
/* we now start execution in SYSTEM mode */
/* This is exactly like USER mode (same stack) */
/* but SYSTEM mode has more privileges */
msr CPSR_c, #ARM_MODE_SYS|I_BIT|F_BIT /* switch to System Mode */
mov sp, r0 /* set stack pointer for SYS mode */
/* we now start execution in SYSTEM mode */
/* This is exactly like USER mode (same stack) */
/* but SYSTEM mode has more privileges */
/* copy initialized variables .data section (Copy from ROM to RAM) */
/* copy initialized variables .data section (Copy from ROM to RAM) */
ldr R1, =_etext
ldr R2, =_data
ldr R3, =_edata
1: cmp R2, R3
1: cmp R2, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo 1b
/* Clear uninitialized variables .bss section (Zero init) */
/* Clear uninitialized variables .bss section (Zero init) */
mov R0, #0
ldr R1, =_bss_start
ldr R2, =_bss_end
2: cmp R1, R2
2: cmp R1, R2
strlo R0, [R1], #4
blo 2b
/* Enter the C code */
/* Enter the C code */
b main
/* ======================================================================== */
/* Function: AT91F_Irq_Handler */
/* */
/* This IRQ_Handler supports nested interrupts (an IRQ interrupt can itself */
/* be interrupted). */
/* */
/* Function: AT91F_Irq_Handler */
/* */
/* This IRQ_Handler supports nested interrupts (an IRQ interrupt can itself */
/* be interrupted). */
/* */
/* This handler re-enables interrupts and switches to "Supervisor" mode to */
/* prevent any corruption to the link and IP registers. */
/* */
/* prevent any corruption to the link and IP registers. */
/* */
/* The Interrupt Vector Register (AIC_IVR) is read to determine the address */
/* of the required interrupt service routine. The ISR routine can be a */
/* standard C function since this handler minds all the save/restore */
/* protocols. */
/* */
/* */
/* Programmers: */
/* of the required interrupt service routine. The ISR routine can be a */
/* standard C function since this handler minds all the save/restore */
/* protocols. */
/* */
/* */
/* Programmers: */
/*--------------------------------------------------------------------------*/
/* ATMEL Microcontroller Software Support - ROUSSET - */
/*--------------------------------------------------------------------------*/
@@ -223,97 +223,97 @@ _init_reset:
/* Object : Generic CStartup to AT91SAM7S256 */
/* 1.0 09/May/06 JPP : Creation */
/* */
/* */
/* */
/* Note: taken from Atmel web site (www.at91.com) */
/* Keil example project: AT91SAM7S-Interrupt_SAM7S */
/* Keil example project: AT91SAM7S-Interrupt_SAM7S */
/* ======================================================================== */
AT91F_Irq_Handler:
/* Manage Exception Entry */
/* Manage Exception Entry */
/* Adjust and save LR_irq in IRQ stack */
sub lr, lr, #4
stmfd sp!, {lr}
sub lr, lr, #4
stmfd sp!, {lr}
/* Save r0 and SPSR (need to be saved for nested interrupt) */
mrs r14, SPSR
stmfd sp!, {r0,r14}
mrs r14, SPSR
stmfd sp!, {r0,r14}
/* Write in the IVR to support Protect Mode */
/* No effect in Normal Mode */
/* Write in the IVR to support Protect Mode */
/* No effect in Normal Mode */
/* De-assert the NIRQ and clear the source in Protect Mode */
ldr r14, =AT91C_BASE_AIC
ldr r0 , [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
ldr r14, =AT91C_BASE_AIC
ldr r0 , [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
/* Enable Interrupt and Switch in Supervisor Mode */
msr CPSR_c, #ARM_MODE_SVC
msr CPSR_c, #ARM_MODE_SVC
/* Save scratch/used registers and LR in User Stack */
stmfd sp!, { r1-r3, r12, r14}
stmfd sp!, { r1-r3, r12, r14}
/* Branch to the routine pointed by the AIC_IVR */
mov r14, pc
bx r0
mov r14, pc
bx r0
/* Manage Exception Exit */
/* Manage Exception Exit */
/* Restore scratch/used registers and LR from User Stack */
ldmia sp!, { r1-r3, r12, r14}
ldmia sp!, { r1-r3, r12, r14}
/* Disable Interrupt and switch back in IRQ mode */
msr CPSR_c, #I_BIT | ARM_MODE_IRQ
msr CPSR_c, #I_BIT | ARM_MODE_IRQ
/* Mark the End of Interrupt on the AIC */
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
/* Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r0,r14}
msr SPSR_cxsf, r14
ldmia sp!, {r0,r14}
msr SPSR_cxsf, r14
/* Restore adjusted LR_irq from IRQ stack directly in the PC */
ldmia sp!, {pc}^
ldmia sp!, {pc}^
/* ======================================================================== */
/* Function: AT91F_Dabt_Handler */
/* */
/* Entered on Data Abort exception. */
/* Enters blink routine (3 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* Function: AT91F_Dabt_Handler */
/* */
/* Entered on Data Abort exception. */
/* Enters blink routine (3 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ======================================================================== */
AT91F_Dabt_Handler: mov R0, #3
b blinker
AT91F_Dabt_Handler: mov R0, #3
b blinker
/* ======================================================================== */
/* Function: AT91F_Pabt_Handler */
/* */
/* Entered on Prefetch Abort exception. */
/* Enters blink routine (2 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* Function: AT91F_Pabt_Handler */
/* */
/* Entered on Prefetch Abort exception. */
/* Enters blink routine (2 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ======================================================================== */
AT91F_Pabt_Handler: mov R0, #2
b blinker
AT91F_Pabt_Handler: mov R0, #2
b blinker
/* ======================================================================== */
/* Function: AT91F_Undef_Handler */
/* */
/* Entered on Undefined Instruction exception. */
/* Enters blink routine (1 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* Function: AT91F_Undef_Handler */
/* */
/* Entered on Undefined Instruction exception. */
/* Enters blink routine (1 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ======================================================================== */
AT91F_Undef_Handler: mov R0, #1
b blinker
AT91F_Undef_Handler: mov R0, #1
b blinker
AT91F_Default_FIQ_handler: b AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler: b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler: b AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler: b AT91F_Default_IRQ_handler
AT91F_Spurious_handler: b AT91F_Spurious_handler
AT91F_Spurious_handler: b AT91F_Spurious_handler
.end
ports/at91sam7s/netport.c
+3 -3
View File
@@ -50,7 +50,7 @@ struct object_data Object_List[BACNET_NETWORK_PORTS_MAX];
#define BACNET_NETWORK_PORT_INSTANCE 1
#endif
/* BACnetARRAY of REAL, is an array of the link speeds
/* BACnetARRAY of REAL, is an array of the link speeds
supported by this network port */
static uint32_t Link_Speeds[] = {9600, 19200, 38400, 57600, 76800, 115200 };
@@ -372,8 +372,8 @@ static int Network_Port_Link_Speeds_Encode(
/**
* @brief Set the device link speed (baud rate)
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @return true if value was set
*/
bool Network_Port_Link_Speed_Set(uint32_t object_instance, float value)
ports/at91sam7s/readme.txt
+10 -10
View File
@@ -1,10 +1,10 @@
This port was done with a AT91SAM7S-EK which contained a
AT91SAM7S64 processor. The compiler was the GNU ARM compiler
and tools from Yagarto project.
and tools from Yagarto project.
The hardware was modified by severing the I-PA5 (RXD0),
I-PA6 (TXD0), I-PA7 (RTS0) pads and rerouting those
signals to a DS75176 RS-485 transceiver.
The hardware was modified by severing the I-PA5 (RXD0),
I-PA6 (TXD0), I-PA7 (RTS0) pads and rerouting those
signals to a DS75176 RS-485 transceiver.
PIN SIGNAL AT91SAM7S
--- ------ ---------
1 RO RXD0
@@ -20,18 +20,18 @@ The makefile allows you to build just the dlmstp or a simple
server, both for programming into the flash memory of the processor.
The dlmstp is the datalink layer for MS/TP over RS-485.
I used the makefile from the command line on Windows, and
then used the SAM-BA to send the resulting .bin file to the
board using a J-Link. To debug the code from flash, run the
I used the makefile from the command line on Windows, and
then used the SAM-BA to send the resulting .bin file to the
board using a J-Link. To debug the code from flash, run the
J-Link GDB Server and then:
> arm-elf-gdb bacnet.elf
I got the crt.s, at91sam7s256.ld, blinker.c, init.c, isr.c, and
timer.c from James P Lynch. I created the rs485.c based on the
initialization sequence from serial.c by Keil Electronik. I
timer.c from James P Lynch. I created the rs485.c based on the
initialization sequence from serial.c by Keil Electronik. I
got the at91sam7s256.h file from Atmel via the Keil website.
I started with the makefile from James P Lynch, but it didn't work
for me. I then used some ideas from FreeRTOS makefile, and
for me. I then used some ideas from FreeRTOS makefile, and
created my own makefile from scratch.
Hopefully you find it useful!
ports/atmega168/bacnet.ewp
+3 -3
View File
@@ -216,7 +216,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m328 ATmega328</state>
<state>m328 ATmega328</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -1279,7 +1279,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m168 ATmega168</state>
<state>m168 ATmega168</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -2341,7 +2341,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m328 ATmega328</state>
<state>m328 ATmega328</state>
</option>
<option>
<name>OGProductVersion</name>
ports/atmega168/bacnet.eww
-2
View File
@@ -6,5 +6,3 @@
</project>
<batchBuild/>
</workspace>
ports/bdk-atxx4-mstp/bacnet.ewp
+4 -4
View File
@@ -216,7 +216,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m644p ATmega644P</state>
<state>m644p ATmega644P</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -1282,7 +1282,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m1284p ATmega1284P</state>
<state>m1284p ATmega1284P</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -2348,7 +2348,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m644p ATmega644P</state>
<state>m644p ATmega644P</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -3414,7 +3414,7 @@
</option>
<option>
<name>GenDeviceSelectMenu</name>
<state>m1284p ATmega1284P</state>
<state>m1284p ATmega1284P</state>
</option>
<option>
<name>OGProductVersion</name>
ports/bdk-atxx4-mstp/bacnet.eww
-2
View File
@@ -6,5 +6,3 @@
</project>
<batchBuild/>
</workspace>
ports/bdk-atxx4-mstp/device.c
+1 -1
View File
@@ -269,7 +269,7 @@ static char *Device_Name_Default(void)
{
static char text[32]; /* okay for single thread */
snprintf(text, sizeof(text), "DEVICE-%lu",
snprintf(text, sizeof(text), "DEVICE-%lu",
(unsigned long)Object_Instance_Number);
return text;
ports/bdk-atxx4-mstp/netport.c
+3 -3
View File
@@ -51,7 +51,7 @@ struct object_data Object_List[BACNET_NETWORK_PORTS_MAX];
#define BACNET_NETWORK_PORT_INSTANCE 1
#endif
/* BACnetARRAY of REAL, is an array of the link speeds
/* BACnetARRAY of REAL, is an array of the link speeds
supported by this network port */
static uint32_t Link_Speeds[] = {9600, 19200, 38400, 57600, 76800, 115200 };
@@ -373,8 +373,8 @@ static int Network_Port_Link_Speeds_Encode(
/**
* @brief Set the device link speed (baud rate)
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @return true if value was set
*/
bool Network_Port_Link_Speed_Set(uint32_t object_instance, float value)
ports/bdk-atxx4-mstp/rs485.c
+1 -1
View File
@@ -3,7 +3,7 @@
* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
*
* SPDX-License-Identifier: MIT
*
*
*********************************************************************/
#include <stdbool.h>
#include <stdint.h>
ports/bdk-atxx4-mstp/test.c
+1 -1
View File
@@ -190,7 +190,7 @@ void test_task(void)
serial_bytes_send((uint8_t *)Send_Buffer, strlen(Send_Buffer));
break;
case 'm':
snprintf(Send_Buffer, sizeof(Send_Buffer),
snprintf(Send_Buffer, sizeof(Send_Buffer),
"\r\nMax:%u", (unsigned)dlmstp_max_master());
serial_bytes_send((uint8_t *)Send_Buffer, strlen(Send_Buffer));
break;
ports/bdk-atxx4-mstp/watchdog.c
+1 -1
View File
@@ -3,7 +3,7 @@
* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
*
* SPDX-License-Identifier: MIT
*
*
*********************************************************************/
#include "hardware.h"
#include "watchdog.h"
ports/esp32/platformio.ini
+1 -1
View File
@@ -16,4 +16,4 @@ framework = espidf
upload_port = COM7
upload_speed = 1152000
monitor_baud = 115200
monitor_baud = 115200
ports/esp32/readme.txt
+49 -49
View File
@@ -1,6 +1,6 @@
Bacnet Server for Espressif ESP32
Steve Karg Bacnet stack using PlatformIO open source ecosystem for IoT development on VSCode or Atom
F. Chaxel 2017
Steve Karg Bacnet stack using PlatformIO open source ecosystem for IoT development on VSCode or Atom
F. Chaxel 2017
TODO list :
@@ -13,55 +13,55 @@ Goto lib/stack and copy the requested files from Steve code :
all .h from include directory (not all required by it's simple)
these .c files from src or demo/handlers
abort.c
address.c
apdu.c
bacaddr.c
bacapp.c
bacdcode.c
bacerror.c
bacint.c
bacreal.c
bacstr.c
bip.c
bvlc.c
cov.c
datetime.c
bacdevobjpropref.c
dcc.c
debug.c
h_cov.c
h_ucov.c
h_npdu.c
h_rp.c
h_rpm.c
h_whois.c
h_wp.c
iam.c
hostnport.c
lighting.c
memcopy.c
noserv.c
npdu.c
proplist.c
reject.c
rp.c
rpm.c
s_iam.c
tsm.c
whois.c
wp.c
abort.c
address.c
apdu.c
bacaddr.c
bacapp.c
bacdcode.c
bacerror.c
bacint.c
bacreal.c
bacstr.c
bip.c
bvlc.c
cov.c
datetime.c
bacdevobjpropref.c
dcc.c
debug.c
h_cov.c
h_ucov.c
h_npdu.c
h_rp.c
h_rpm.c
h_whois.c
h_wp.c
iam.c
hostnport.c
lighting.c
memcopy.c
noserv.c
npdu.c
proplist.c
reject.c
rp.c
rpm.c
s_iam.c
tsm.c
whois.c
wp.c
Modify
in config.h
MAX_TSM_TRANSACTIONS 255, set the value to 10 for instances
in main.c
wifi_config to fit your wifi network
BACNET_LED 5, set another IO number depending of your board
in config.h
MAX_TSM_TRANSACTIONS 255, set the value to 10 for instances
in main.c
wifi_config to fit your wifi network
BACNET_LED 5, set another IO number depending of your board
A lot of Warning will be issued at compile time due to the redefinition of BIT macros.
Could be removes by placing a #ifndef #BIT0 .. #endif arround the BIT macro in bits.h,
Could be removes by placing a #ifndef #BIT0 .. #endif arround the BIT macro in bits.h,
and moving to the top of include list
#include "bacnet/datalink/datalink.h" in tsm.c, s_iam and in device.c
#include "bacport.h" in bip.c and in bip.h (redondant include in bip.c)
#include "bacnet/datalink/bvlc.h" in bvlc.c
#include "bacnet/datalink/datalink.h" in tsm.c, s_iam and in device.c
#include "bacport.h" in bip.c and in bip.h (redondant include in bip.c)
#include "bacnet/datalink/bvlc.h" in bvlc.c
ports/esp32/src/ai.c
+1 -1
View File
@@ -323,7 +323,7 @@ void Analog_Input_Out_Of_Service_Set(uint32_t object_instance, bool value)
index = Analog_Input_Instance_To_Index(object_instance);
if (index < MAX_ANALOG_INPUTS) {
/* BACnet Testing Observed Incident oi00104
/* BACnet Testing Observed Incident oi00104
The Changed flag was not being set when a client wrote to the
Out-of-Service bit. Revealed by BACnet Test Client v1.8.16 (
www.bac-test.com/bacnet-test-client-download ) BC 135.1: 8.2.1-A BC
ports/esp32/src/bip_init.c
+1 -1
View File
@@ -53,4 +53,4 @@ bool bip_init(char *ifname)
bip_set_socket(sock);
return true;
}
}
ports/linux/bacnet_ipv6.lua
+12 -12
View File
@@ -56,7 +56,7 @@ do
[0x82]="B/IPv6 (Annex X)"
}
local t_BACnetBIPV6_Functions = {
-- Annex X, PPR3 Draft 22
-- Annex X, PPR3 Draft 22
[0x00]="BVLC-Result",
[0x01]="Original-Unicast-NPDU",
[0x02]="Original-Broadcast-NPDU",
@@ -69,7 +69,7 @@ do
[0x09]="Register-Foreign-Device",
[0x0A]="Delete-Foreign-Device",
[0x0B]="Secure-BVLL",
[0x0C]="Distribute-Broadcast-To-Network"
[0x0C]="Distribute-Broadcast-To-Network"
}
local pf_BIPV6Data = ProtoField.bytes ("BIPV6.data", "B/IPV6 Data")
@@ -121,14 +121,14 @@ do
local ti_BIPV6 = {}
ti_BIPV6.ti = tree:add(p_BACnetBIPV6,buffer(0))
offset, v_BIPV6.Type, ti_BIPV6.Type = uint_dissector(ti_BIPV6.ti, pf_BIPV6.Type, buffer, offset, 1)
--if v_BIPV6.Type == 0x81 then
-- p_dissector_bipv4:call(buffer, pkt, tree)
-- elseif v_BIPV6 ~= 0x82 then
-- ti_BIPV6.Type:add_expert_info(PI_MALFORMED, PI_WARN, "Unknown BVLC Type")
--if v_BIPV6.Type == 0x81 then
-- p_dissector_bipv4:call(buffer, pkt, tree)
-- elseif v_BIPV6 ~= 0x82 then
-- ti_BIPV6.Type:add_expert_info(PI_MALFORMED, PI_WARN, "Unknown BVLC Type")
-- return
--end
--end
if v_BIPV6.Type ~= 0x82 then
ti_BIPV6.Type:add_expert_info(PI_MALFORMED, PI_WARN, "Unknown BVLC Type")
ti_BIPV6.Type:add_expert_info(PI_MALFORMED, PI_WARN, "Unknown BVLC Type")
return
end
offset, v_BIPV6.Function, ti_BIPV6.Function = uint_dissector(ti_BIPV6.ti, pf_BIPV6.Function, buffer, offset, 1)
@@ -148,7 +148,7 @@ do
p_dissector_bacnet:call(npduData:tvb(), pkt, tree)
end
end
-- CLB don't show the raw data
-- CLB don't show the raw data
-- if offset ~= buffer:len() then
-- ti_BIPV6.ti:add(pf_BIPV6Data,buffer(offset))
-- end
@@ -187,7 +187,7 @@ do
t_BACnetBIPV6_dissectors[0x04] = function(buffer,pkt,tree,offset,npdu)
offset = bytes_dissector(tree,pf_BIPV6.OriginalSourceVirtualAddress,buffer,offset,3)
offset = bytes_dissector(tree,pf_BIPV6.DestinationVirtualAddress,buffer,offset,3)
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
offset = bytes_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_ip,buffer,offset,16)
offset = uint_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_port,buffer,offset,2)
return offset
@@ -215,7 +215,7 @@ do
-- [0x08] Forwarded-NPDU
t_BACnetBIPV6_dissectors[0x08] = function(buffer,pkt,tree,offset,npdu)
offset = bytes_dissector(tree,pf_BIPV6.OriginalSourceVirtualAddress,buffer,offset,3)
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
offset = bytes_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_ip,buffer,offset,16)
offset = uint_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_port,buffer,offset,2)
return offset, buffer(offset)
@@ -243,7 +243,7 @@ do
-- [0x0C] Distribute-Broadcast-To-Network
t_BACnetBIPV6_dissectors[0x0C] = function(buffer,pkt,tree,offset,npdu)
offset = bytes_dissector(tree,pf_BIPV6.OriginalSourceVirtualAddress,buffer,offset,3)
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
local subtree = tree:add(pf_BIPV6.OriginalSourceEffectiveAddress,buffer(offset,18))
offset = bytes_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_ip,buffer,offset,16)
offset = uint_dissector(subtree,pf_BIPV6.OriginalSourceEffectiveAddress_port,buffer,offset,2)
return offset, buffer(offset)
ports/linux/bacport.h
+29 -29
View File
@@ -10,47 +10,47 @@
#define BACPORT_H
/* common unix sockets headers needed */
#include <sys/types.h> /* basic system data types */
#include <sys/time.h> /* timeval{} for select() */
#include <time.h> /* timespec{} for pselect() */
#include <netinet/in.h> /* sockaddr_in{} and other Internet defns */
#include <arpa/inet.h> /* inet(3) functions */
#include <fcntl.h> /* for nonblocking */
#include <netdb.h>
#include <errno.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h> /* for S_xxx file mode constants */
#include <sys/uio.h> /* for iovec{} and readv/writev */
#include <unistd.h>
#include <sys/wait.h>
#include <sys/un.h> /* for Unix domain sockets */
#include <sys/types.h> /* basic system data types */
#include <sys/time.h> /* timeval{} for select() */
#include <time.h> /* timespec{} for pselect() */
#include <netinet/in.h> /* sockaddr_in{} and other Internet defns */
#include <arpa/inet.h> /* inet(3) functions */
#include <fcntl.h> /* for nonblocking */
#include <netdb.h>
#include <errno.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h> /* for S_xxx file mode constants */
#include <sys/uio.h> /* for iovec{} and readv/writev */
#include <unistd.h>
#include <sys/wait.h>
#include <sys/un.h> /* for Unix domain sockets */
#ifdef HAVE_SYS_SELECT_H
#include <sys/select.h> /* for convenience */
#ifdef HAVE_SYS_SELECT_H
#include <sys/select.h> /* for convenience */
#endif
#ifdef HAVE_POLL_H
#include <poll.h> /* for convenience */
#ifdef HAVE_POLL_H
#include <poll.h> /* for convenience */
#endif
#ifdef HAVE_STRINGS_H
#include <strings.h> /* for convenience */
#ifdef HAVE_STRINGS_H
#include <strings.h> /* for convenience */
#endif
/* Three headers are normally needed for socket/file ioctl's:
* <sys/ioctl.h>, <sys/filio.h>, and <sys/sockio.h>.
*/
#ifdef HAVE_SYS_IOCTL_H
#include <sys/ioctl.h>
#ifdef HAVE_SYS_IOCTL_H
#include <sys/ioctl.h>
#endif
#ifdef HAVE_SYS_FILIO_H
#include <sys/filio.h>
#ifdef HAVE_SYS_FILIO_H
#include <sys/filio.h>
#endif
#ifdef HAVE_SYS_SOCKIO_H
#include <sys/sockio.h>
#ifdef HAVE_SYS_SOCKIO_H
#include <sys/sockio.h>
#endif
#include <pthread.h>
ports/linux/bip6.c
+1 -1
View File
@@ -25,7 +25,7 @@ static bool BIP6_Debug = false;
/**
* @brief Conditionally use the debug_printf function
*
*
* @param stream - file stream to print to
* @param format - printf format string
* @param ... - variable arguments
ports/linux/dlmstp.c
+1 -1
View File
@@ -118,7 +118,7 @@ static int timespec_subtract(
*
* @param ts - The time to which to add to.
* @param ns - The number of nanoseconds to add. Allowed range
* is -NS_PER_S..NS_PER_S (i.e., plus minus one second).
* is -NS_PER_S..NS_PER_S (i.e., plus minus one second).
*/
static void timespec_add_ns(struct timespec *ts, long ns)
{
ports/linux/dlmstp.mak
+5 -5
View File
@@ -3,7 +3,7 @@ CC = gcc
BASEDIR = .
# -g for debugging with gdb
DEFINES = -DBIG_ENDIAN=0 -DBACDL_MSTP=1 -DTEST_DLMSTP
INCLUDES = -I. -I../../
INCLUDES = -I. -I../../
CFLAGS = -Wall $(INCLUDES) $(DEFINES) -g
SRCS = rs485.c \
@@ -16,17 +16,17 @@ OBJS = ${SRCS:.c=.o}
TARGET = dlmstp
all: ${TARGET}
${TARGET}: ${OBJS}
${CC} -pthread -o $@ ${OBJS}
${CC} -pthread -o $@ ${OBJS}
.c.o:
${CC} -c ${CFLAGS} $*.c -o $@
depend:
rm -f .depend
${CC} -MM ${CFLAGS} *.c >> .depend
clean:
rm -rf core ${TARGET} $(OBJS) *.bak *.1 *.ini
ports/linux/readme.txt
+1 -1
View File
@@ -1,2 +1,2 @@
This is a port to Linux for testing.
The unit tests can be run via the test.sh script.
The unit tests can be run via the test.sh script.
ports/lwip/README.md
+2 -2
View File
@@ -1,9 +1,9 @@
## Port of BACnet/IP to LwIP 2.x
This LwIP BACnet/IP port uses a Makefile designed to be used from
the continuous integration pipeline. The container is configured with
the continuous integration pipeline. The container is configured with
Ubuntu Linux and uses APT to install liblwip-dev library and header files.
This build method ensures that the code is valid for the particular LwIP
This build method ensures that the code is valid for the particular LwIP
library that is released with Ubuntu.
## Integration Hints
ports/pic18f6720/pic18f6720.tpi
+7 -7
View File
@@ -35,19 +35,19 @@ BIBBs Supported:
-- SCHED-A SCHED-I-B SCHED-E-B
-- T-VMT-A T-VMT-I-B T-VMT-E-B
-- T-ATR-A T-ATR-B
-- DM-DDB-A
-- DM-DDB-A
DM-DDB-B
-- DM-DOB-A
-- DM-DOB-A
-- DM-DOB-B
-- DM-DCC-A
-- DM-DCC-A
DM-DCC-B
-- DM-PT-A DM-PT-B
-- DM-TM-A DM-TM-B
-- DM-TS-A
-- DM-TS-A
-- DM-TS-B
-- DM-UTC-A
-- DM-UTC-A
-- DM-UTC-B
-- DM-RD-A
-- DM-RD-A
DM-RD-B
-- DM-BR-A DM-BR-B
-- DM-R-A DM-R-B
@@ -139,7 +139,7 @@ Data Link Layer Option:
-- ISO 8802-3, 10BASET
-- ISO 8802-3, Fiber
-- ARCNET, coax star
-- ARCNET, coax bus
-- ARCNET, coax bus
-- ARCNET, twisted pair star
-- ARCNET, twisted pair bus
-- ARCNET, fiber star
ports/pic18f6720/readme.txt
-1
View File
@@ -40,4 +40,3 @@ DATABANK NAME=stackreg START=0xC00 END=0xDFF PROTECTED
//STACK SIZE=0x100 RAM=gpr13
STACK SIZE=0x200 RAM=stackreg
ports/pic18f97j60/readme.txt
-1
View File
@@ -40,4 +40,3 @@ DATABANK NAME=stackreg START=0xC00 END=0xDFF PROTECTED
//STACK SIZE=0x100 RAM=gpr13
STACK SIZE=0x200 RAM=stackreg
ports/rx62n/device.c
+1 -1
View File
@@ -781,7 +781,7 @@ int Device_Read_Property_Local(BACNET_READ_PROPERTY_DATA *rpdata)
* If the Object or Property can't be found, sets the error class and code.
*
* @param rpdata [in,out] Structure with the desired Object and Property info
* on entry, and APDU message on return.
* on entry, and APDU message on return.
* @return The length of the APDU on success, else BACNET_STATUS_ERROR
*/
int Device_Read_Property(BACNET_READ_PROPERTY_DATA *rpdata)
ports/stm32f10x/CMakeLists.txt
+6 -6
View File
@@ -1,5 +1,5 @@
# This is a CMake example for STM32 ARM Cortex-M3 STM32F103RGT6 on
# a STM32 Discovery Kit evaluation board using the ARM GCC compiler
# a STM32 Discovery Kit evaluation board using the ARM GCC compiler
# and STM32 CMSIS library.
#
# Board STM32F103 Discovery Kit
@@ -234,13 +234,13 @@ target_compile_definitions(${EXECUTABLE} PRIVATE
# inhibit pedantic warnings
target_compile_options(${EXECUTABLE} PRIVATE
-Wall -Wextra -pedantic
-Wfloat-equal -Wconversion -Wredundant-decls
-Wfloat-equal -Wconversion -Wredundant-decls
-Wswitch-default
# don't warn about conversion, sign, compares, long long and attributes
# since they are common in embedded
-Wno-sign-conversion
-Wno-sign-conversion
-Wno-conversion
-Wno-sign-compare
-Wno-sign-compare
-Wno-long-long
-Wno-attributes
# don't warn about implicit fallthrough since it is common in network protocols
@@ -296,7 +296,7 @@ add_custom_target(symbols
)
# calculate the worst case CSTACK memory usage by size and place into a file
add_custom_target(cstack
add_custom_target(cstack
DEPENDS ${EXECUTABLE}
COMMENT "Print CSTACK memory depth by size"
COMMAND ${CMAKE_CSTACK} ${EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR} 1> ${PROJECT_NAME}.su
@@ -306,7 +306,7 @@ add_custom_target(cstack
)
# Print file and library sizes
add_custom_target(memmap
add_custom_target(memmap
DEPENDS ${PROJECT_NAME}.map
COMMENT "Print file and library memory usage by size"
COMMAND ${CMAKE_MEMAP} -t GCC_ARM ${PROJECT_NAME}.map
ports/stm32f10x/Makefile
+1 -1
View File
@@ -231,7 +231,7 @@ ram-usage:
@$(NM) -t d -S --size-sort $(TARGET).elf 1> $(TARGET).nm
@echo "=ADDRESS= ==SIZE== = ==VARIABLE NAME=="
@tail $(TARGET).nm
.PHONY: cstack
cstack:
@$(CSTACK_TOOL) $(COBJ) 2> /dev/null 1> $(TARGET).su
ports/stm32f10x/STM32_BACnet_Demo.svg
-1
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After

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ports/stm32f10x/STM32_BACnet_Software.svg
-1
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After

Width:  |  Height:  |  Size: 162 KiB

ports/stm32f10x/bacnet.ewp
+2 -2
View File
@@ -78,7 +78,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>STM32F103ZG ST STM32F103ZG</state>
<state>STM32F103ZG ST STM32F103ZG</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@@ -138,7 +138,7 @@
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>STM32F103ZG ST STM32F103ZG</state>
<state>STM32F103ZG ST STM32F103ZG</state>
</option>
<option>
<name>FPU2</name>
ports/stm32f10x/bacnet.eww
-2
View File
@@ -6,5 +6,3 @@
</project>
<batchBuild/>
</workspace>
ports/stm32f10x/netport.c
+3 -3
View File
@@ -50,7 +50,7 @@ struct object_data Object_List[BACNET_NETWORK_PORTS_MAX];
#define BACNET_NETWORK_PORT_INSTANCE 1
#endif
/* BACnetARRAY of REAL, is an array of the link speeds
/* BACnetARRAY of REAL, is an array of the link speeds
supported by this network port */
static uint32_t Link_Speeds[] = {9600, 19200, 38400, 57600, 76800, 115200 };
@@ -372,8 +372,8 @@ static int Network_Port_Link_Speeds_Encode(
/**
* @brief Set the device link speed (baud rate)
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @return true if value was set
*/
bool Network_Port_Link_Speed_Set(uint32_t object_instance, float value)
ports/stm32f10x/readme.txt
+14 -14
View File
@@ -1,31 +1,31 @@
This port was done with the STM32 ARM Cortex-M3 STM32F103RGT6 on
This port was done with the STM32 ARM Cortex-M3 STM32F103RGT6 on
a STM32 Discovery Kit using the STM32 CMSIS library and drivers
and IAR EWARM 6.10 compiler.
The CMSIS library was 21MiB compressed, so I didn't include it
as part of this project. The CMSIS and drivers
as part of this project. The CMSIS and drivers
can be found by following the 'Click here for STM32
embedded firmware' link from the resources page:
http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelector&doctype=FIRMWARE&SubClassID=1169
There will be a list of firmware resources.
The library you are looking for is in the
There will be a list of firmware resources.
The library you are looking for is in the
‘ARM-based 32-bit MCU STM32F10xxx standard peripheral library’.
Download the
‘ARM-based 32-bit MCU STM32F10xxx standard peripheral library’
and the CMSIS library can be found in
'…\STM32F10x_StdPeriph_Lib_V3.4.0\Libraries\CMSIS\CM3'.
Download the
‘ARM-based 32-bit MCU STM32F10xxx standard peripheral library’
and the CMSIS library can be found in
'…\STM32F10x_StdPeriph_Lib_V3.4.0\Libraries\CMSIS\CM3'.
Copy the contents of 'CMSIS' to the 'CMSIS' folder in this project.
and the drivers library can be found in
'…\STM32F10x_StdPeriph_Lib_V3.4.0\Libraries\STM32F10x_StdPeriph_Driver'.
Copy the contents of 'STM32F10x_StdPeriph_Driver' to the
and the drivers library can be found in
'…\STM32F10x_StdPeriph_Lib_V3.4.0\Libraries\STM32F10x_StdPeriph_Driver'.
Copy the contents of 'STM32F10x_StdPeriph_Driver' to the
'drivers' folder in this project.
The hardware interface only uses the USART and a peripheral pin
(RTS) for the MS/TP RS-485 interface, and the System Clock for
(RTS) for the MS/TP RS-485 interface, and the System Clock for
the millisecond timer.
It was created for the STM32 Design Challenge on March 20, 2011,
by Steve Karg. Although the design didn't win any awards,
it was one of the six finalists and was on display at the
by Steve Karg. Although the design didn't win any awards,
it was one of the six finalists and was on display at the
STM booth at the 2010 Embedded Systems Conference West.
http://www.stm32challenge.com/
ports/stm32f10x/stm32f10x.ld
+14 -14
View File
@@ -22,10 +22,10 @@ SECTIONS
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_etext = .;
_sidata = _etext;
_sidata = _etext;
PROVIDE(etext = .);
_fini = . ;
*(.fini)
_fini = . ;
*(.fini)
} >flash
@@ -40,20 +40,20 @@ SECTIONS
_edata = .;
} >sram
.ARM.extab :
{
*(.ARM.extab*)
} >sram
.ARM.extab :
{
*(.ARM.extab*)
} >sram
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx*)
} >sram
__exidx_end = .;
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx*)
} >sram
__exidx_end = .;
.bss (NOLOAD) : {
. = ALIGN(4);
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss .bss.*)
ports/stm32f10x/stm32f10x_conf.h
+1 -1
View File
@@ -47,7 +47,7 @@
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
/* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#include "stm32f10x_misc.h"
#include "stm32f10x_misc.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
ports/stm32f10x/stm32f10x_flash.icf
+1 -1
View File
@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
block CSTACK, block HEAP };
ports/stm32f10x/system_stm32f10x.c
+1 -1
View File
@@ -397,7 +397,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f10x_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on
* This function configures the external SRAM mounted on
* STM3210E-EVAL board (STM32 High density devices). This SRAM will be used as
* program data memory (including heap and stack).
* @param None
ports/stm32f4xx/.vscode/launch.json
Vendored
+1 -1
View File
@@ -46,4 +46,4 @@
"showDevDebugOutput": "raw"
}
]
}
}
ports/stm32f4xx/CMakeLists.txt
+5 -5
View File
@@ -244,13 +244,13 @@ target_compile_definitions(${EXECUTABLE} PRIVATE
# inhibit pedantic warnings
target_compile_options(${EXECUTABLE} PRIVATE
-Wall -Wextra -pedantic
-Wfloat-equal -Wconversion -Wredundant-decls
-Wfloat-equal -Wconversion -Wredundant-decls
-Wswitch-default
# don't warn about conversion, sign, compares, long long and attributes
# since they are common in embedded
-Wno-sign-conversion
-Wno-sign-conversion
-Wno-conversion
-Wno-sign-compare
-Wno-sign-compare
-Wno-long-long
-Wno-attributes
# don't warn about implicit fallthrough since it is common in network protocols
@@ -307,7 +307,7 @@ add_custom_target(symbols
)
# calculate the worst case CSTACK memory usage by size and place into a file
add_custom_target(cstack
add_custom_target(cstack
DEPENDS ${EXECUTABLE}
COMMENT "Print CSTACK memory depth by size"
COMMAND ${CMAKE_CSTACK} ${EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR} 1> ${PROJECT_NAME}.su
@@ -317,7 +317,7 @@ add_custom_target(cstack
)
# Print file and library sizes
add_custom_target(memmap
add_custom_target(memmap
DEPENDS ${PROJECT_NAME}.map
COMMENT "Print file and library memory usage by size"
COMMAND ${CMAKE_MEMAP} -t GCC_ARM ${PROJECT_NAME}.map
ports/stm32f4xx/Makefile
+1 -1
View File
@@ -251,7 +251,7 @@ ram-usage:
@$(NM) -t d -S --size-sort $(TARGET).elf 1> $(TARGET).nm
@echo "=ADDRESS= ==SIZE== = ==VARIABLE NAME=="
@tail $(TARGET).nm
.PHONY: cstack
cstack:
@$(CSTACK_TOOL) $(COBJ) 2> /dev/null 1> $(TARGET).su
ports/stm32f4xx/README.md
+3 -3
View File
@@ -85,12 +85,12 @@ For debugging, install these tools:
#### CMake & Visual Studio Code
There is a CMakeLists.txt file that enables building the project with the
tools that CMake can find. It is useful under Visual Studio Code editor
with the CMake Tools extension for quickly configuring the build environment,
tools that CMake can find. It is useful under Visual Studio Code editor
with the CMake Tools extension for quickly configuring the build environment,
choosing a cross-compiler, and building.
For Visual Studio Code debugging, add the Cortex-Debug extension, and configure
its settings for the specific OS and path of the tools. For Windows using
its settings for the specific OS and path of the tools. For Windows using
MinGW64:
"cortex-debug.armToolchainPath.windows": "C:/msys64/mingw64/bin",
ports/stm32f4xx/bacnet.c
+2 -2
View File
@@ -66,11 +66,11 @@ static uint32_t Device_ID = 0xFFFFFFFF;
#define BACNET_MULTISTATE_VALUES_MAX 12
#endif
/**
/**
* @brief Initialize the BACnet device object, the service handlers, and timers
*/
void bacnet_init(void)
{
{
uint32_t instance;
/* initialize objects */
Device_Init(NULL);
ports/stm32f4xx/bacnet.ewp
+2 -2
View File
@@ -78,7 +78,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>STM32F429ZI ST STM32F429ZI</state>
<state>STM32F429ZI ST STM32F429ZI</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@@ -138,7 +138,7 @@
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>STM32F429ZI ST STM32F429ZI</state>
<state>STM32F429ZI ST STM32F429ZI</state>
</option>
<option>
<name>FPU2</name>
ports/stm32f4xx/docs/Arduino_RS485_Shield_SKU_DFR0259.htm
+6 -6
View File
@@ -2,12 +2,12 @@
<html lang="zh-CN">
<!-- Header -->
<head>
<title>
Arduino_RS485_Shield_SKU__DFR0259-DFRobot
</title>
<meta name="description" content="wiki:Thiis RS485 shield designed for the Arduino is able to convert UART/Serial to RS48. This board allows Arduino communicate with industrial device." />
<meta name="keywords" content="RS485 Shield wiki, arduino shield wiki, arduino rs485 shield wiki" />
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1, user-scalable=no">
<title>
Arduino_RS485_Shield_SKU__DFR0259-DFRobot
</title>
<meta name="description" content="wiki:Thiis RS485 shield designed for the Arduino is able to convert UART/Serial to RS48. This board allows Arduino communicate with industrial device." />
<meta name="keywords" content="RS485 Shield wiki, arduino shield wiki, arduino rs485 shield wiki" />
<meta name="viewport" content="width=device-width, initial-scale=1, maximum-scale=1, user-scalable=no">
</head>
<body>
ports/stm32f4xx/netport.c
+2 -2
View File
@@ -377,8 +377,8 @@ static int Network_Port_Link_Speeds_Encode(
/**
* @brief Set the device link speed (baud rate)
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @return true if value was set
*/
bool Network_Port_Link_Speed_Set(uint32_t object_instance, float value)
ports/stm32f4xx/stm32f429.svd
+2 -2
View File
@@ -10,7 +10,7 @@
<fpuPresent>false</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
@@ -43116,4 +43116,4 @@
</registers>
</peripheral>
</peripherals>
</device>
</device>
ports/stm32f4xx/stm32f4xx.icf
+1 -1
View File
@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
block CSTACK, block HEAP };
ports/stm32f4xx/stm32f4xx.ld
+1 -1
View File
@@ -5,7 +5,7 @@ MEMORY
}
_estack = 0x20000000 + 128k - 4; /* End of SRAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 48K;
/* Analysis from MAP file and Stack Usage (su) +
ports/stm32f4xx/stm32f4xx_it.c
+5 -5
View File
@@ -1,11 +1,11 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f4xx_it.c
* @file IO_Toggle/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
@@ -19,7 +19,7 @@
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_it.h"
@@ -31,7 +31,7 @@
/** @addtogroup IO_Toggle
* @{
*/
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -151,6 +151,6 @@ void PendSV_Handler(void)
/**
* @}
*/
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
ports/stm32f4xx/stm32f4xx_it.h
+3 -3
View File
@@ -1,6 +1,6 @@
/**
******************************************************************************
* @file GPIO/IOToggle/stm32f4xx_it.h
* @file GPIO/IOToggle/stm32f4xx_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
@@ -17,7 +17,7 @@
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
@@ -25,7 +25,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
ports/stm32f4xx/system_stm32f4xx.c
+150 -150
View File
@@ -4,16 +4,16 @@
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* by the user application to setup the SysTick
* timer or configure other parameters.
*
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
@@ -55,8 +55,8 @@
/** @addtogroup stm32f4xx_system
* @{
*/
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
@@ -64,7 +64,7 @@
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
@@ -96,7 +96,7 @@
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
@@ -106,7 +106,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
@@ -148,7 +148,7 @@ void assert_failed(
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
@@ -165,7 +165,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
@@ -178,7 +178,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
@@ -191,7 +191,7 @@ void SystemInit(void)
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
@@ -207,41 +207,41 @@ void SystemInit(void)
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@@ -257,10 +257,10 @@ void SystemCoreClockUpdate(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
@@ -298,10 +298,10 @@ void SystemCoreClockUpdate(void)
static void System_Delay_Milliseconds(uint32_t mdelay)
{
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
do
do
{
__NOP();
}
}
while (Delay --);
}
@@ -369,79 +369,79 @@ void SystemInit_ExtMemCtl(void)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
@@ -449,50 +449,50 @@ void SystemInit_ExtMemCtl(void)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@@ -500,7 +500,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
@@ -508,7 +508,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
(void)(tmp);
(void)(tmp);
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
@@ -534,13 +534,13 @@ void SystemInit_ExtMemCtl(void)
clock */
RCC->AHB1ENR |= 0x0000007D;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */
#endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000;
@@ -570,78 +570,78 @@ void SystemInit_ExtMemCtl(void)
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
@@ -651,65 +651,65 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
@@ -724,55 +724,55 @@ void SystemInit_ExtMemCtl(void)
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
@@ -784,7 +784,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@@ -805,8 +805,8 @@ void SystemInit_ExtMemCtl(void)
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp);
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp);
}
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
ports/stm32f4xx/system_stm32f4xx.h
+10 -10
View File
@@ -4,8 +4,8 @@
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@@ -16,8 +16,8 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
@@ -25,8 +25,8 @@
/** @addtogroup stm32f4xx_system
* @{
*/
*/
/**
* @brief Define to prevent recursive inclusion
*/
@@ -35,7 +35,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/** @addtogroup STM32F4xx_System_Includes
* @{
@@ -76,7 +76,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
/** @addtogroup STM32F4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void System_LSE_Init(void);
@@ -94,8 +94,8 @@ extern void System_LSE_Init(void);
/**
* @}
*/
/**
* @}
*/
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
ports/win32/README.md
+3 -3
View File
@@ -6,8 +6,8 @@ and the (free) Microsoft Visual Studio Community Edition
## Building with Makefile under MinGW32
Note: Building for 64-bit with MinGW64 requires extra runtimes,
whereas building for 32-bit as Win32 doesn't require any other
Note: Building for 64-bit with MinGW64 requires extra runtimes,
whereas building for 32-bit as Win32 doesn't require any other
files for the EXE to work in any version of Windows.
* MSYS2 installation is (from powershell):
@@ -41,7 +41,7 @@ files for the EXE to work in any version of Windows.
* Verify make is built for Windows32:
make --version
Built for Windows32
## Building and running with Microsoft Visual Studio
ports/win32/borland.bat
-2
View File
@@ -3,5 +3,3 @@ echo Build for Borland 5.5 tools
set BORLAND_DIR=c:\borland\bcc55
%BORLAND_DIR%\bin\make -f makefile.mak clean
%BORLAND_DIR%\bin\make -f makefile.mak all
ports/win32/dlmstp-mm.c
+1 -1
View File
@@ -52,7 +52,7 @@ static uint16_t Timer_Silence(void *arg)
uint32_t now = timeGetTime();
uint32_t delta_time = 0;
(void)arg;
(void)arg;
if (SilenceStartTime < now) {
delta_time = now - SilenceStartTime;
} else {
ports/win32/rs485.mak
+3 -3
View File
@@ -92,8 +92,8 @@ clean :
# Compiler configuration file
$(BCC_CFG) :
Copy &&|
$(CFLAGS)
-c
$(CFLAGS)
-c
-y #include line numbers in OBJ's
-v #include debug info
-w+ #turn on all warnings
@@ -107,4 +107,4 @@ $(CFLAGS)
-w-sig # ignore warning conversion may lose sig digits
| $@
# EOF: makefile
# EOF: makefile
ports/win32/setvars.bat
-1
View File
@@ -1,2 +1 @@
set BORLAND_DIR=\bcc55
ports/xplained/device.c
+1 -1
View File
@@ -226,7 +226,7 @@ static char *Device_Name_Default(void)
{
static char text[32]; /* okay for single thread */
snprintf(text, sizeof(text), "DEVICE-%lu",
snprintf(text, sizeof(text), "DEVICE-%lu",
(unsigned long)Object_Instance_Number);
return text;
ports/xplained/led.h
+1 -1
View File
@@ -44,7 +44,7 @@ extern "C" {
void);
#else
/* dummy stubs */
#define led_on(x)
#define led_on(x)
#define led_on_interval(x, ms)
#define led_off(x)
#define led_off_delay(x, ms)
ports/xplained/netport.c
+3 -3
View File
@@ -44,7 +44,7 @@ struct object_data Object_List[BACNET_NETWORK_PORTS_MAX];
#define BACNET_NETWORK_PORT_INSTANCE 1
#endif
/* BACnetARRAY of REAL, is an array of the link speeds
/* BACnetARRAY of REAL, is an array of the link speeds
supported by this network port */
static uint32_t Link_Speeds[] = {9600, 19200, 38400, 57600, 76800, 115200 };
@@ -366,8 +366,8 @@ static int Network_Port_Link_Speeds_Encode(
/**
* @brief Set the device link speed (baud rate)
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @param object_instance The object instance number of the object
* @param value The new link speed value
* @return true if value was set
*/
bool Network_Port_Link_Speed_Set(uint32_t object_instance, float value)
ports/xplained/nvmdata.h
+1 -1
View File
@@ -15,7 +15,7 @@
eeprom_write_block((uint8_t *)(src),(uint8_t *)(dst), (size_t)(len))
#define nvm_read(src, dst, len) \
eeprom_read_block((uint8_t *)dst, (const uint8_t *)(src),(size_t)(len))
eeprom_read_block((uint8_t *)dst, (const uint8_t *)(src),(size_t)(len))
/*=============== EEPROM ================*/
/* define EEPROM signature version */
ports/xplained/readme.txt
+1 -1
View File
@@ -17,4 +17,4 @@ to use the I/O that you want to use, and not worry about the
"CONF_BOARD_ENABLE_RS485_XPLAINED". Or you can leave the
"CONF_BOARD_ENABLE_RS485_XPLAINED" in the files so that you can
always test on the XPLAINED platform with Debug-XPLAINED, and use
"Debug" or "Release" for your project.
"Debug" or "Release" for your project.
ports/zephyr/bacnet-config.h
+2 -2
View File
@@ -4,9 +4,9 @@
* @author Steve Karg
* @date 2024
* @section LICENSE
*
*
* Copyright (C) 2024 Steve Karg <skarg@users.sourceforge.net>
*
*
* SPDX-License-Identifier: MIT
*/
#ifndef BACNET_PORTS_ZEPHYR_BACNET_CONFIG_H
ports/zephyr/bip-init.c
+2 -2
View File
@@ -146,8 +146,8 @@ void bip_get_broadcast_address(BACNET_ADDRESS *dest)
}
/**
* @brief Set the BACnet/IP address
* @param addr - network IPv4 address
* @brief Set the BACnet/IP address
* @param addr - network IPv4 address
* @return true if the address was set
*/
bool bip_set_addr(BACNET_IP_ADDRESS *addr)
ports/zephyr/bip6-init.c
+2 -2
View File
@@ -141,7 +141,7 @@ void bip6_set_interface(char *ifname)
NET_IF_MAX_IPV6_ADDR - 1);
return;
}
LOG_INF("BIP6: Using configured index %d",
LOG_INF("BIP6: Using configured index %d",
CONFIG_BACDL_BIP6_ADDRESS_INDEX);
memcpy(
&unicast.address,
@@ -340,7 +340,7 @@ static int bvlc6_snprintf_addr(char *s, size_t n, BACNET_IP6_ADDRESS *addr)
bvlc6_address_get(
addr, &addr16[0], &addr16[1], &addr16[2], &addr16[3], &addr16[4],
&addr16[5], &addr16[6], &addr16[7]);
return snprintf(s, n, "%04X:%04X:%04X:%04X:%04X:%04X:%04X:%04X",
addr16[0], addr16[1], addr16[2], addr16[3], addr16[4], addr16[5],
addr16[6], addr16[7]);
ports/zephyr/mstimer-init.c
-1
View File
@@ -28,4 +28,3 @@ void mstimer_init(void)
{
}